1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of forming metal layers and other layers and avoiding peeling in the back-ending process to form semiconductor devices.
2. Description of the Related Art
When semiconductor integrated circuits are fabricated, several methods are used to form multi-layer structures to offer different functions such as conductor layer, dielectric layer, insulating layer or adhesion layer. The structures use various materials to make the device achieve the best efficiency. In present semiconductor industry, tungsten silicide has those advantages of high melting point, high stability and low resistance. It is mostly used to enhance the ohmic contact between polysilicon layers and used as partial metal layer of a gate in the metal oxide semiconductor (MOS).
A dielectric layer is provided between a tungsten silicide layer and a metal layer during the back-ending process to form a tungsten silicide layer. It is easy to find the tungsten silicide layer and the metal layer contacting directly and peeling in the wafer edge and the mark number section which is used to distinguish a wafer. A titanium/titanium nitride layer is usually formed on the oxide layer to enhance the metal adhesion of the oxide layer before forming the metal layer. The titanium nitride layer has a bad adhesion of the polysilicon layer and the tungsten silicide layer. When they touch each other directly, they peel and form particles. The particles contaminate the devices and the holo-machine and affect the process.
FIG. 1 is a cross-sectional view of a tungsten silicide layer contacting with a metal layer. A conductive layer 102 and an oxide layer 104 are formed on a semiconductor device 100. A titanium/titanium nitride layer 106 and a metal layer 108 are formed on the oxide layer 104. The oxide layer 104 may not completely cover the conductive layer 102 at the edge of the semiconductor device 100. That makes a region 100 nearing the wafer edge of the conductive layer 102 contacting with the titanium/titanium nitride layer 106 and metal layer 108. Since the adhesion between etch layer is poor, the metal layer 108 or the titanium/titanium nitride layer may peel and form particles to contaminate the process and the machine. This phenomenon doesn't only happen at the wafer edge but also at the mark number used to distinguish the wafer.